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The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits

The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits


IC designers appraise currently MOS transistor geometries and currents to compromise objectives like gain-bandwidth, slew-rate, dynamic range, noise, non-linear distortion, etc. Making optimal choices is a difficult task. How to minimize for insta...


Streckkod 9780387471006
Kategori Böcker > Naturvetenskap & teknik > Teknik > Elektronik & kommunikationsteknik > Elektronik > Kretsar & komponenter